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Posted: April 12, 2000
Written by: Tuan "Solace" Nguyen
RISC Meets CISC
RISC = Reduced Instruction Set Computing
CISC = Complex Instruction Set Computing
The CISC architecture has been around for a very long time and is considered by many to be "80's" technology. Interestingly, Intel has pushed that technology so much that it kept up with the rest. Quite an amazing feat from the engineers over at Intel actually.
RISC technology is newer than CISC and has been around from the 90's and is the choice architecture for high-end processors. Because of the "Reduced Instruction Set", the instructions are more optimized and efficient to program for. Executing for the CISC set requires more time but can be just as fast.
Current Intel processors are CISC based but deploy a different approach to executing the instructions. They fetch the instructions as CISC instructions then decode them to RISC instructions for faster processing. Overall, this enhances the performance of the processor because the same thing can be done in less time.
How the Athlon does it
The Athlon is a decoupled micro architectured processor. This is a method of mixing modern RISC principles to the older CISC architecture like the x86. The Athlon will convert funky CISC to more streamlined RISC instructions. These instructions are called ROPs or RISC Operations. This conversion happens internally to stay compatible with existing x86 software. This is very efficient in super-scalar pipelined processors (those that can process more than 1 instruction per clock cycle or per hertz).
The Athlon does this by executing the ROPs out of order. The CPU changes the order of a program's instructions while it's running and can achieve as many as nine ROPs per clock cycle. Other processors can do this too! But, the Athlon pulverizes them all. It can shuffle around as many as 72 instructions while deciding how to arrange them to execute more efficiently.
Check out the comparison. AMD vs. Intel... fight!
During this out-of-order execution, the Athlon's FPUs (floating point unit) are blistering away as many as three instructions simultaneously. Two instructions can be a mixture of MMX, 3DNow! or 80-bit math operations. The FPUs in the Pentium III can do either a multiply or an add during any cycle. On the other hand, the Athlon can do a multiply and an add simultaneously. The maximum floating point throughput at 650MHz is about 1.2 GigaFLOPs (1.2 billion FP operations per second!) with 80-bit math ops and 2.4 GigaFLOPs with MMX or 3DNow! shot in the arm.
So show me some benchmarks!